TMS320VC5409APGE16

Product Summary

The TMS320VC5409APGE16 is a kind of fixed-point, digital signal processor (DSP). The device is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Parametrics

Absolute maximum ratings: (1)DVDD, Supply voltage I/O range: – 0.3 V to 4.0 V; (2)CVDD, Supply voltage core range: – 0.3 V to 2.0 V; (3)VI, Input voltage range: – 0.3 V to 4.5 V; (4)VO, Output voltage range: – 0.3 V to 4.5 V; (5)TC, Operating case temperature range: – 40℃ to 100℃; (6)Tstg, Storage temperature range: – 55℃ to 150℃.

Features

Features: (1)Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent Bank-Switching 40-Bit Accumulators; (2)17-17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation; (3)Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator; (4)Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle; (5)Data Bus With a Bus Holder Feature; (6)Enhanced External Parallel Interface (XIO2); (7)Single-Instruction-Repeat and Block-Repeat Operations for Program Code; (8)Block-Memory-Move Instructions for Better Program and Data Management; (9)Instructions With a 32-Bit Long Word Operand; (10)Instructions With Two- or Three-Operand Reads ; (11)Arithmetic Instructions With Parallel Store Parallel Load ; (12)Conditional Store Instructions Fast Return From Interrupt; (13)Power Consumption Control With IDLE1,; (14)Two Address Generators With Eight Auxiliary IDLE2, and IDLE3 Instructions With Registers and Two Auxiliary Register Power-Down Modes Arithmetic Units (ARAUs) ; (15)CLKOUT Off Control to Disable CLKOUT; (16)Data Bus With a Bus Holder Feature ; (17)On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic.

Diagrams

<IMG alt="TMS320VC5409APGE16" src="http://www.seekic.com/uploadfile/ic-mfg/2011418204413676.jpg" border=0>